Cache and Memory Hierarchy Design
A widely read and authoritative book for hardware and software designers. This innovative book exposes the characteristics of performance-optimal single- and multi-level cache hierarchies by approaching the cache design process through the novel perspective of minimizing execution time.Figure 8.10 shows the circuit diagram of a basic sense amplifier. More complex sense amplifiers in modern DRAM devices contain the basic elements shown in Figure 8.10, as well as additional circuit elements for array isolation, carefulanbsp;...
| Title | : | Cache and Memory Hierarchy Design |
| Author | : | Steven A. Przybylski |
| Publisher | : | Morgan Kaufmann - 1990 |
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